1. Field of the Invention
The present invention relates generally to power metal oxide semiconductor (MOS) transistors and, more particularly, to surge protection techniques for use therewith.
2. Related Art
Generally, power MOS transistors for use in land vehicles including but not limited to power MOS field effect transistors (MOSFETS) are strictly required to offer low turn-on resistivity and high withstanding voltage rating at low costs.
Power MOSFETs as built in hybrid integrated circuit (IC) devices for land vehicles typically include vertical type power MOSFETs (up-drain type) and lateral type power MOSFETs (LDMOS type).
Such power MOSFETs are adaptable for use in driving loads such as lamps, relay switches and the like, and are often encountered with a variety of kinds of surge voltages or noises as applied via output terminals thereof, including electrostatic potential variations, inductive (xe2x80x9cLxe2x80x9d) loads, and others. To avoid problems due to such surge noises, power MOSFETs are required to offer enhanced surge withstand rating or durability in addition to high breakdown voltages and low turn-on resistivity.
A prior known approach to increasing surge withstand rating for protecting power MOS transistors against possible surge voltages in particular from electrostatic discharge (ESD) noises is to employ certain methodology including (i) a method for strengthening power elements per se by increasing the impurity concentration of a channel well region to thereby suppress operability of parasitic transistors, (ii) a method for providing a trigger circuit including a capacitor between the drain and gate of a MOS transistor to thereby permit a surge current to flow therein through a MOS operation, and (iii) a surge bypass method with a capacitor or power Zener diode or else being additionally connected in parallel to a power MOSFET of interest (see FIG. 20).
While the prior art approach exhibits advantages, these do not come without accompanying penalties which follow. The methods (i), (ii) stated above suffer from a problem that the turn-on resistance of a power MOS transistor can increase with an increase in threshold voltage Vth and also a problem that the expected ESD surge withstand rating is variable with a change in size of a power MOS transistor per se in view of the current capacity thereof. Problems faced with the surge bypass method (iii) are such that the requisite number of externally associated IC components is increased and that the ESD withstand rating is lowered due to the presence of a parasitic or stray inductance (see FIG. 20) of electrical interconnect leads involved.
An improved scheme is disclosed in Published Unexamined Japanese Patent Application No. 10-4180, which permits the surge withstand rating to stay unchanged in a way independent of sizes of power elements and electrical leads or else. This technique will be explained in detail with reference to FIG. 21.
FIG. 21 shows an LDMOS transistor of the so-called xe2x80x9cresurfxe2x80x9d structure type with its unique ESD remedy for employing a built-in protective diode D11, which is provided at an outer peripheral portion of such LDMOS structure for breaking down at a certain withstand voltage level that is potentially lower than that of an internal cell(s). And, any surface current incoming from the drain side is forced to flow through the protective diode toward the source side and then dumped away externally.
Unfortunately, this structure is still with a room for further improvement. More specifically, this structure is inherently designed to employ the resurf-type structure utilizing the same lightly-doped p-type (xe2x80x9cLDpxe2x80x9d) well region 800 for both its LDMOS cell unit and protective diode unit, which structure has its breakdown voltage as determined depending on the impurity concentration and diffusion depth of a lightly-doped n-type (LDn) well region 801 overlying the LDp well region 800. Due to this design scheme, the LDMOS cell unit measures approximately 70 volts in breakdown voltage whereas the protective diode D11 is about 60 volts in breakdown voltage since this diode comes with a drain region 802 that is further laminated on the LDn well region 801 in the cell unit, resulting in a potential difference between them being as small as about 10 volts.
Also note that in the structure of FIG. 21, the protective diode D11""s p-type layer 800 acting as an anode region is disposed between the LDn well region 801 (or alternatively n-type drain region 802) and n-type layers 803, 804 to provide the so-called pinch resistor structure; for this reason, the resulting sheet resistance is as high as about 10 kilo-ohms per unit area (kxcexa9/xe2x96xa1).
Further, the structure of FIG. 21 is such that since an n-type epitaxial layer 104 is present beneath the protective diode D11, the diode is far from any ideal or xe2x80x9cpurexe2x80x9d diode structure, which also includes a parasitic npn transistor having a collector formed of an n-type region with the LDn well region 801 and n-type drain region 802 overlapping each other, a base formed of its underlying LDp well layer 800, and an emitter of a lightly doped n (n+) type layer 804 of a substrate. With such an arrangement, an increase in surge current would result in an increase in voltage potential of such parasitic transistor""s p-type base layer, which in turn leads to occurrence of a bipolar operation. In other words, the protective diode D11 will be readily destructive by local current concentration due to such bipolar operation.
This invention has been conceived in view of the background thus far described and its first object is to provide a new and improved power MOS transistor with a protective diode that is high in breakdown voltage difference and yet less in sheet resistivity.
In accordance with a first aspect of the invention, the above object is attainable by providing an up-drain type MOSFET, characterized in that a base region of a second conductivity type so that the base partly overlaps a deep drain region, and that this base region is connected to the source side thereby forming a surge bypassing diode between the source and drain.
In accordance with a second aspect of the invention, an up-drain type MOSFET is provided which is featured in that a semiconductor region of a first conductivity type is formed in a surface of a surface-side semiconductor layer while forming a base region of a second conductivity type in such a manner as to partly overlap this semiconductor region, and that the base region is connected to the source side whereas the semiconductor region of the first conductivity type is connected to the drain side thereby forming a surge bypassing diode between the source and drain.
In accordance with a third aspect of the invention, an LDMOSFET is provided, which is featured in that a semiconductor region of a first conductivity type is formed in a surface of a surface-side semiconductor layer while forming a base region of a second conductivity type so that it partly overlaps this semiconductor layer, and that the base region is connected to the source side whereas the semiconductor region of the first conductivity type is connected to the drain side thereby forming a surge bypassing diode between the source and drain.
In accordance with a fourth aspect of the invention, a VDMOSFET is provided, which features in that a deep region of first conductivity type is formed which is deep enough to reach a semiconductor substrate from the a surface of a surface-side semiconductor layer while at the same time forming in the surface of the surface-side semiconductor layer a base region of second conductivity type which partly overlaps the deep region, and that the base region is connected to the source side thus forming a surge bypassing diode between the source and drain.
In accordance with a fifth aspect of the invention, a lateral type insulated gate bipolar transistor (IGBT) is provided, which features in that a semiconductor region of first conductivity type is formed in a surface of a surface-side semiconductor layer while simultaneously forming a base region of second conductivity type so that it partly overlaps the semiconductor region, and that the base region is connected to the source side whereas the semiconductor region is coupled to the collector side thus forming a surge bypassing diode between the emitter and collector.
With use of any one of the device structures stated supra, the resultant source cell unit (or emitter cell unit) is increased in breakdown voltage when compared to those MOS structures of the so-called resurf type in virtue of field curvature relax effects due to cell integrationxe2x80x94typically, as high as about 120 volts. On the other hand, the breakdown voltage of the surge bypass diode for use as the intended protective diode may be lowered in valuexe2x80x94e.g. 70 volts or belowxe2x80x94because of the fact that it is determinable in value by a distance or spatial interval between two adjacent diffusion regions. In short, it becomes possible to design the protective diode""s breakdown voltage in a way independent of the cell unit, which in turn makes it possible to provide a sufficiently increased breakdown voltage difference.
Furthermore, the formation of the intended diode by use of two diffusion regions makes it possible to reduce or minimize the sheet resistance of an anode in the presence of the base region (e.g. as low as 200xcexa9/xe2x96xa1, or more or less), which in turn enables the protective diode to much decrease in operating resistance than the device of FIG. 21. Moreover, the protective diode is hardly affectable by current concentration effect occurring due to bipolar operations, leading to appreciable improvement in breakdown level.
With the above-noted principles of the invention, it is possible to achieve an improved power MOS transistor having its protective diode with increased breakdown voltage difference and reduced sheet resistivity.
In accordance with a sixth aspect of the invention, a double-well complementary MOS (CMOS) transistor structure is provided, which employs two separate well regions of first and second conductivity types that are also formed in a power device formation region and bipolar transistor formation region respectively. More than one power device and bipolar transistor are constituted in such well regions.
It is thus possible to fabricate in a semiconductor substrate any intended power device and bipolar transistor while using none of the power device""s exclusive-use mask and bipolar transistor""s dedicated mask. This in turn makes it possible to reduce costs for manufacturing a semiconductor device with power devices and bipolar CMOS (xe2x80x9cBiCMOSxe2x80x9d) transistors formed in the same semiconductor substrate.
In accordance with a seventh aspect of the invention, a first mask as disposed over a semiconductor substrate is used to simultaneously fabricate those well regions of a first conductivity type in respective formation regions of a power device and a bipolar transistor plus a double-well CMOS transistor. Further, a second mask is disposed overlying the semiconductor substrate for use in simultaneously forming well regions of a second conductivity type in respective formation regions of the power device and bipolar transistor plus double-well CMOS transistor. Thereafter, gate electrodes are disposed simultaneously in the formation regions of such power device and double-well CMOS transistor.
With the manufacturing method above, it is possible to fabricate in the semiconductor substrate more than one power device and bipolar transistor without using any exclusive-use or xe2x80x9cdedicatedxe2x80x9d masks of the power device and bipolar transistor. This in turn makes it possible to reduce production costs of a semiconductor device with such power device and BiCMOS transistor formed in the same semiconductor substrate.